Planar magnetic tunnel junction substrate having recessed alignment marks
US7241668B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 2003 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Jun 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an alignment mark structure for a semiconductor device includes forming an alignment recess at a selected level of the semiconductor device substrate. A first metal layer is formed over the selected substrate level and within the alignment recess, wherein the alignment recess is formed at a depth such that the first metal layer only partially fills the alignment recess. A second metal layer is formed over the first metal layer such that the alignment recess is completely filled. The second metal layer and the first metal layer are then planarized down to the selected substrate level, thereby creating a sacrificial plug of the second layer material within the alignment recess. The sacrificial plug is removed in a manner so as not to substantially roughen the planarized surface at the selected substrate level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.