Structure and fabrication method for capacitors integratible with vertical replacement gate transistors
US7242056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2004 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Apr 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/047
Abstract
A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate. In an associated method of manufacture, a first device region, selected from the group consisting of the source region and a drain region of a field-effect transistor is formed on a semicon…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.