Semiconductor structure

US7242071B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Xuefeng Liu · Gaithersburg, US
• Robert M. Rassel · Colchester, US
• Steven H. Voldman · South Burlington, US

Key dates

• Filing date: Jul 6, 2006
• Grant date: Jul 10, 2007
• Expiry date: Jul 6, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/854

Abstract

A structure comprises a deep sub-collector buried in a first epitaxial layer and a near sub-collector buried in a second epitaxial layer. The structure further comprises a deep trench isolation structure isolating a region which is substantially above the deep sub-collector, a reach-through structure in contact with the near sub-collector, and a reach-through structure in contact with the deep sub-collector to provide a low-resistance shunt, which prevents COMS latch-up of a device. The method includes forming a merged triple well double epitaxy/double sub-collector structure.