Stacked package structure
US7242081B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 24, 2006 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Apr 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked package structure and a method for manufacturing the same are disclosed. The package structure comprises: a substrate having a first surface and a second surface in opposition to each other; at least one chip deposed on and electrically connected to the first surface of the substrate; a plurality of electrical connection devices deposed on the first surface and periphery of the substrate, wherein each electrical connection device is higher than the at least one chip in altitude; and an encapsulant covering the first surface of the substrate, the at least one chip and the electrical connection devices, wherein a top end of each electrical connection device is exposed at a surface of the encapsulant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.