System and method for testing integrated circuits
US7242209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2004 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Jun 12, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31928
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A module (236, 236′) containing an integrated testing system (108) that includes one or more measurement engines (200, 202) tightly coupled with a compute engine (208). The one or more measurement engines include at least one stimulus instrument (212) for exciting circuitry of a device-under-test (104) with one or more stimulus signals, and at least one measurement instrument (216) that measures the response of the device-under-test to the stimulus signal(s) and generates measurement data. The compute engine includes computation logic circuitry (800) for determining whether or not the circuitry aboard the device-under-test passes or fails. The integrated testing system further includes a communications engine (204) providing two-way communications between the integrated testing system automated testing equipment (116) and/or a dedicated user interface (140) residing on a host computer (136).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.