Method and circuit for reading and writing an instruction buffer
US7243170B2 · kind B2 · utility
0Cited by
6References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2003 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Apr 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3814
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction buffer and a method of buffering instructions. The instruction buffer including: a memory array partitioned into multiple identical memory sub-arrays arranged in sequential order from a first memory sub-array to a last memory sub-array, each memory sub-array having multiple instruction entry positions and adapted to store a different instruction of a set of concurrent instructions in a single instruction entry position of any one of the memory sub-arrays, the set of concurrent instructions arranged in sequential order from a first instruction to a last instruction
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.