Pipeline circuit for low latency memory
US7243203B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 13, 2003 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Apr 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1039
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The embodiments herein describe a memory device and method for reading and writing data. In one embodiment, a memory device is provided comprising a memory array and first and second data buffers in communication with the memory array. The second data buffer comprises a larger storage capacity than the first data buffer. During a write operation, data is stored in the second data buffer and then stored in the memory array. During a read operation, data is read from the memory array and then stored in the first data buffer but not in the second data buffer. Because the smaller-storage-capacity buffer takes less time to fill than the larger-storage-capacity buffer, there is less of a delay in outputting data from the memory device as compared to memory devices that use a larger-storage-capacity buffer for both read and write operations. Other embodiments are provided, and each of the embodiments can be used alone or in combination with one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.