Apparatus and method for speeding up access time of a large register file with wrap capability
US7243209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2005 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Jan 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30098
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.