Stall optimization for an in-order, multi-stage processor pipeline which analyzes current and next instructions to determine if a stall is necessary
US7243214B2 · kind B2 · utility
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7References
11Claims
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Key dates
| Filing date | Apr 21, 2003 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Jun 14, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3873
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to some embodiments, a method determining a number of stages associated with an instruction to be executed via a processor pipeline, determining a number of stages associated with a subsequent instruction, and stalling the pipeline based on the number of stages associated with the instruction to be executed and the number of stages associated with the subsequent instruction is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.