Method and apparatus for controlling a processor in a data processing system
US7243221B1 · kind B1 · utility
13Cited by
2References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 26, 2004 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | May 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for controlling a processor in a data processing system is described. In an example, the processor is maintained in a halt condition in response to reset information received from the data processing system (200) (e.g., initialization of an integrated circuit having a processor embedded therein). At least one memory resource in communication with the processor is configured. The processor is then released from the halt condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.