Test masks for lithographic and etch processes
US7243316B2 · kind B2 · utility
218Cited by
66References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2002 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Dec 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated by the lithographic or etch process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.