Integrated circuit chip design
US7243323B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Jan 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method of developing a model of a circuit design including the steps of generating four different path-tracing runs, creating four arcs from the four different path-tracing runs, and combining the four arcs into two separate models. Also, a method of adjusting timing of a clock signal provided to a first block and a second block where data signals travel via a first path from the first block to the second block and data signals travel via a second path from the second block to the first block and the time for the data signals to travel the first path is greater than the time for the data signals to travel the second path. The clock signal provided to the second block relative to the clock signal provided to the first block is delayed by an amount that is a function of the difference between the time for the data signals to travel the first path and the time for the data signals to travel the second path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.