Fabrication of an OTP-EPROM having reduced leakage current
US7244651B2 · kind B2 · utility
4Cited by
17References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2003 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | May 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/637
Abstract
The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be achieved by blocking implantation of the Vtp implant into a channel region of an n-well that substantially underlies a floating gate structure. The Vtp implant can be blocked by providing a mask overlying the surface of the channel region of the n-well during implantation of the Vtp implant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.