Integration of strained Ge into advanced CMOS technology

US7244958B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Huiling Shang · Bethlehem, US
• Meikei Ieong · Wappingers Falls, US
• Jack O. Chu · Manhasset Hills, US
• Kathryn Guarini · Yorktown Heights, US

Key dates

• Filing date: Jun 24, 2004
• Grant date: Jul 17, 2007
• Expiry date: Jun 24, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/711

Abstract

A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.