Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode
US7244983B2 · kind B2 · utility
6Cited by
11References
14Claims
0Family size
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Key dates
| Filing date | Apr 23, 2003 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Aug 1, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/932
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for an on-chip decoupling capacitor. The capacitor includes a bottom electrode that consist of nanostructures deposited over a planarized metal, a dielectric material deposited over the nanostructures, and a top electrode deposited over the dielectric material. The shape of the bottom electrode is tunable by modulating the diameter and/or the length of the nanostructures to produce an increase in capacitance without increasing the footprint of the on-chip decoupling capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.