Nonvolatile semiconductor memory including two memory cell columns sharing a single bit line
US7244984B2 · kind B2 · utility
18Cited by
1References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 16, 2004 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Jul 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This nonvolatile semiconductor memory includes: a first and a second memory cell column having memory cell transistors connected in series with a floating gate and a first and a second control gate located at both sides of that floating gate; a first select-gate transistor connected between the first memory cell column and a bit line; a second select-gate transistor connected between the second memory cell column and the bit line; and a third select gate transistor connected between the first memory cell column and a source line and also between the second memory cell column and the source line, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.