Clock regulation apparatus and circuit arrangement
US7245167B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 16, 2004 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Nov 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Clock regulation apparatus for preventing a logic switching mechanism from operating incorrectly. The apparatus has a supply voltage input that receives a supply voltage, which is also applied to the logic switching mechanism, a comparison unit that outputs an error signal if the supply voltage value drops below a reference value, a clock signal input that receives a clock signal from a clock generator, and a clock suppression unit, which is coupled to the clock signal input and to the comparison unit, that has a clock output for outputting the clock signal and that suppresses or delays the clock signal for a duration of at least one clock period if the error signal exists.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.