Semiconductor device
US7245531B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2005 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Aug 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.