Non-volatile programmable memory cell for programmable logic array
US7245535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2005 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Sep 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.