Reduced area, reduced programming voltage CMOS efuse-based scannable non-volatile memory bitcell
US7245546B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 2006 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | May 9, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip includes a number of memory bitcells. Each bitcell includes: a latch having a sense node; a programming transistor having an efficient saturation region of operation; and a fuse connected to the programming transistor at a first terminal of the fuse. A programming voltage can be supplied to the fuse at a second terminal of the fuse; and a logic gate circuit is connected to the gate of the programming transistor. The logic gate circuit is operated at the programming voltage so that the logic gate circuit drives the programming transistor in the efficient saturation region when programming the fuse. The bitcell also includes a fuse-sensing circuit having no more than one transistor. Operation in the efficient saturation region allows the programming transistor to be small. Combined with using no more than one sensing transistor, significant reduction in area of the bitcells on the chip is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.