Method of avoiding plasma arcing during RIE etching
US7247252B2 · kind B2 · utility
4Cited by
29References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2002 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Dec 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for avoiding plasma arcing during a reactive ion etching (RIE) process including providing a semiconductor wafer having a process surface for depositing a dielectric insulating layer; depositing at least a portion of a dielectric insulating layer to form a deposition layer according to plasma assisted chemical vapor deposition (CVD) process; treating the deposition layer portion with a hydrogen plasma treatment to reduce an electrical charge nonuniformity of the deposition layer including applying a biasing power to the semiconductor wafer; and, carrying out a subsequent reactive ion etching process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.