Method of fabricating semiconductor device using selective epitaxial growth
US7247533B2 · kind B2 · utility
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2References
12Claims
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Key dates
| Filing date | Dec 30, 2004 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Feb 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28562
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device uses selective epitaxial growth (SEG), by which leakage current generation is minimized using lateral SEG growth in case a contact intrudes a shallow track isolation feature. The method includes steps of forming a sidewall spacer on a gate, selectively growing an epitaxial layer in a lateral direction relative to the sidewall spacer and the gate, and forming a contact on the epitaxial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.