Silicon device on Si:C-OI and SGOI and method of manufacture
US7247534B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2003 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Dec 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.