On-chip analysis and computation of transition behavior of embedded nets in integrated circuits
US7248066B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2004 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Dec 29, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus for enabling the on-chip analysis of the voltage and/or current transition behaviour of one or more embedded nets of an integrated circuit independently of the fabrication process. The said apparatus comprises a Reference Step Generator (RSG) for providing programmable reference voltages or currents, a Step Delay Generator (SDG) for providing programmable delays, a Comparator (C) that receives the output of the reference step generator on one input, the output from the node under test at the second input, and a latch enable signal from the step delay generator, and provides a latched digital output in response to the comparison, and a controller that co-ordinates the operation of the reference step generator, Step Delay Generator and Latching Comparator to provide a transient response measurement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.