Method and apparatus for providing security for debug circuitry
US7248069B2 · kind B2 · utility
6Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2003 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Sep 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to debug circuitry (20) and more particularly to a method and apparatus for providing security for debug circuitry (20). In one embodiment, a plurality of non-volatile elements (38) are used in providing selective disabling and re-enabling of at least a portion of the debug circuitry (20). Authentication may also be used. The present invention may use any debug interface, including standard debug interfaces such as the JTAG debug interface defined by the IEEE.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.