Circuit arrangement having security and power saving modes
US7248506B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 31, 2005 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Jan 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuit arrangement having complementary data input nodes for reception of a dual rail data signal and complementary data output nodes for outputting a dual rail data signal. A connection switch is connected to complementary data nodes by means of which the complementary data nodes can be connected to one another with a low resistance, a control unit is provided for generating a first control signal for the connection switch, and the circuit arrangement is designed to be operated in two operating modes, in which case in a power saving mode, the connection switch is switched by the control unit to have a high resistance, and in a security node, the connection switch is switched by the control unit to have a low resistance when the potential at the complementary data nodes is intended to be equalized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.