Globally observing load operations prior to fence instruction and post-serialization modes
US7249245B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2004 |
| Grant date | Jul 24, 2007 |
| Priority date | — |
| Expiry date | Nov 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a memory unit and a processor where the processor has a load buffer to store a first instruction and a cache controller to block the first instruction from dispatch into the cache controller until load data for load operations prior to the first instruction fetched from the memory unit are globally observed. The processor further may include a control register having a first mode storage to store a mode control selection for pre-serialization and a second mode storage to store a mode control selection for post-serialization to enable control of pre-serialization and post-serialization of load operations with respect to the first instruction. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.