Process for forming and analyzing stacked die
US7250310B1 · kind B1 · utility
3Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2004 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | Dec 26, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2898
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a stacked die integrated circuit structure, the structure can subsequently be tested by removing any packaging material and separating the die from a die paddle and from each other. The separation can involve the use of chemicals or heat, with or without the use of mechanical force. One aspect of the invention includes making use of specifically chosen adhesives to secure the die to the die paddle and to each other, so that any subsequent removal can readily be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.