Power transistor arrangement and method for fabricating it
US7250343B2 · kind B2 · utility
31Cited by
7References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2004 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | Mar 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement (1) is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array (3) with cell array trenches (5) each containing a field electrode structure (11) and a gate electrode structure (10). The field electrode structure (11) is electrically conductively connected to the source metallization (15) by a connection trench (6) in the cell array (3).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.