Double-gate FETs (Field Effect Transistors)

US7250347B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Toshiharu Furukawa · South Burlington, US
• Mark C. Hakey · Saint Albans, US
• Steven J. Holmes · Colchester, US
• David V. Horak · South Burlington, US
• Charles W. Koburger, III · Delmar, US
• Peter H. Mitchell · Jericho, US
• Larry Nesbit · Farmington, US

Key dates

• Filing date: Jan 28, 2005
• Grant date: Jul 31, 2007
• Expiry date: Oct 8, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6744

Abstract

A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.