Manufacturing method for strained silicon wafer
US7250357B2 · kind B2 · utility
8Cited by
1References
7Claims
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Key dates
| Filing date | Sep 8, 2005 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | Oct 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02532
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method for producing a stained silicon wafer has the steps of forming an Si1-xGex composition-graded layer of which Ge concentration is stepwisely increased on a single crystal silicon substrate, forming an Si1-xGex uniform composition layer of which Ge concentration is constant on the Si1-xGex composition-graded layer, forming a stain-relaxed Si1-yGey layer of which Ge concentration y is constant while y satisfies relationship of 0.5x≦y<x on the Si1-xGex uniform composition layer and epitaxially growing a strained Si layer on the strain-relaxed Si1-yGey layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.