Chip package having chip extension and method
US7250576B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2005 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | May 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16195
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package including a chip extension for containing thermal interface material (TIM) and improves chip cooling, and a related method, are disclosed. In particular, the chip package includes a chip, a cooling structure coupled to the chip via a TIM, and a chip extension may be thermally coupled to an outer edge of the chip. A TIM placed between the chip and the cooling structure is contained during thermal cycling by the chip extension such that void formation at the edge of the chip, which can move between the chip and cooling structure, is suppressed. The chip extension also improves lateral heat dissipation by providing a greater thermal contact area between the cooling structure and the chip and, if needed, the substrate at a much lower cost than using larger die with lower production unit output from a wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.