SONOS memory device having nano-sized trap elements
US7250653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2004 |
| Grant date | Jul 31, 2007 |
| Priority date | — |
| Expiry date | May 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.