Method of forming a gate insulator in group III-V nitride semiconductor devices
US7253061B2 · kind B2 · utility
20Cited by
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9Claims
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Key dates
| Filing date | Dec 6, 2004 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Oct 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02258
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a gate insulator in the manufacture of a semiconductor device comprises conducting a photo-assisted electrochemical process to form a gate-insulating layer on a gallium nitride layer of the semiconductor device, wherein the gate-insulating layer includes gallium oxynitride and gallium oxide, and performing a rapid thermal annealing process. The photo-assisted electrochemical process uses an electrolyte bath including buffered CH3COOH at a pH between about 5.5 and 7.5. The rapid thermal annealing process is conducted in O2 environment at a temperature between about 500° C. and 800° C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.