Method of fabricating a composite gate dielectric layer
US7253063B2 · kind B2 · utility
1Cited by
32References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 23, 2002 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Mar 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having composite dielectric layer formed between a silicon substrate and a gate electrode. The composite gate dielectric layer including a layer of silicon oxide, SiOx≦2, having a dielectric constant of greater than about 3.9 and about 12 or less, and a complementary dielectric layer for inhibiting the flow of leakage current through the composite dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.