Transistor structure with minimized parasitics and method of fabricating the same
US7253070B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2006 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Jul 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/291
Abstract
A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.