Semiconductor bonding pad structure
US7253531B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2006 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | May 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a bonding pad structure. At least one lower circuit layer is disposed overlying the substrate, wherein the lower circuit layer is a layout of circuit under pad. A top circuit layer is disposed overlying the lower circuit layer, wherein the top circuit layer comprises a top interconnect dielectric layer and a top interconnect pattern in the top interconnect dielectric layer. A top connecting layer is disposed overlying the top circuit layer, electrically connecting the top interconnect pattern. A top pad layer is disposed overlying the top connecting layer. A bonding ball is disposed overlying the top pad layer, wherein sides of the top interconnect pattern do not overlap a region extending inwardly and outwardly from a boundary of the bonding ball within distance of about 2.5μm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.