Memory with selectable single cell or twin cell configuration
US7254089B2 · kind B2 · utility
1Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2004 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Apr 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit comprises a memory including a memory array, a twin cell mode predecoder, and a row address predecoder. The memory array comprises word lines. The twin cell mode predecoder is configured for selecting one of four word line activation configurations for the memory array. The four word line activation configurations include three twin cell word line activation configurations and a single cell word line activation configuration. The row address predecoder is configured for selecting one of four word lines if the single cell word line activation configuration is selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.