Network for decreasing transmit link layer core speed
US7254647B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 23, 2001 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Jul 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a core for providing speed reduction in communications between a transmission media and a processor having an upper link layer in a parallel-serial architecture. The core includes a lower logic layer, serial lanes connecting the logic layer to the transmission media, at least one selector connected to the serial lanes for supporting at least two differing data widths. The logic layer controls the selector, and multiple buffers are interposed in the serial lanes. The selector enables the speed reductions is the upper link layer of the processor. The processor is particularly applicable to interface components used in InfiniBand-type hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.