Processor cache memory as RAM for execution of boot code
US7254676B2 · kind B2 · utility
14Cited by
5References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2002 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Dec 20, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2515
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the executing boot code stream as a memory store.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.