Flash memory test system and method capable of test time reduction
US7254757B2 · kind B2 · utility
4Cited by
13References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2004 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Aug 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory test system capable of test time reduction and an electrical test method using the same: The invention provides a parallel tester that includes a first memory and a second memory. The first and second memories are used to each supply different data to identical addresses within a plurality of DUTs, thereby making it possible to conduct in parallel tests such as trim tests, repair tests, and invalid block masking test. Thus parallel testing is done to replace testing that was previously done serially.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.