Test structures for feature fidelity improvement
US7254803B2 · kind B2 · utility
1Cited by
6References
50Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Aug 7, 2007 |
| Priority date | — |
| Expiry date | Jun 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and techniques for generating test structures. The test structures may conform to a set of design rules for a portion of an integrated circuit design. The test structures may include base figures, which may be in an enriched environment. For example, the test structures may include one or more additional figures such as surrounding figures, external figures, and/or symmetric figures. A correction algorithm for correcting a layout may be checked using a plurality of the test structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.