Flip chip packaging process
US7256066B2 · kind B2 · utility
7Cited by
1References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2005 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Apr 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flip chip packaging process uses an underfill as an encapsultant to reduce the possibility of delamination from occurring due to differential coefficients of thermal expansion, and thus the reliability of a flip chip package structure can be increased. Furthermore, the flooding of the encapsulant over the cutting line need not be taken into consideration for cutting the substrate. Therefore, the usage area of the substrate usage is increased, i.e., more chips can be mounted per unit area of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.