Contact resistance reduction by new barrier stack process
US7256121B2 · kind B2 · utility
5Cited by
10References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2004 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Dec 2, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76865
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.