Differential input receiver having over-voltage protection
US7256652B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2005 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Feb 7, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45322
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential receiver circuit. In one embodiment, the circuit includes first and second input transistors, each having a first terminal coupled to a bias node (a first and second bias node, respectively), as well as first and second bias transistors, each having a first terminal coupled to the first and second bias nodes, respectively. The circuit further includes a first current source coupled to provide current to the first bias node and a second current source coupled to the second bias node. The differential receiver circuit is coupled to first and second, which receive first and second voltages, respectively. The first and second current sources provide current to the first and second bias nodes, respectively, such that the voltage present on the first and second bias nodes remains with approximately a threshold voltage of a midpoint between the voltages present on the first and second voltage nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.