Inverter non-volatile memory cell and array system
US7257033B2 · kind B2 · utility
18Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2005 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Sep 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
NVM arrays include rows and columns of NVM cells comprising a floating gate, dual transistor, inverter storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.