Bit line discharge control method and circuit for a semiconductor memory
US7257039B2 · kind B2 · utility
12Cited by
6References
43Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2004 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Nov 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of controlling a discharge of bit lines of a matrix of memory cells comprises conditioning a value of a current flowing through a bit line of the matrix during a bit line discharge phase to an absence of an indication of defectiveness of the bit line. The method allows preventing crowbar currents that otherwise flow during the bit line discharge phase when a defective bit line exhibits a short-circuit to a defective word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.