Embedded PCI-Express implementation
US7257655B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2004 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Jun 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus provide PCI Express support on a programmable device. A device includes a hard-coded transceiver that supports functionality associated with the PCI Express physical layer and link layer. The hard-coded transceiver can also support part of the PCI Express transaction layer. Soft-coded logic is used to support higher layer functionality including a portion of the transaction layer to allow custom configuration of PCI Express features such as virtual channels, buffers, prioritization, and quality of service characteristics. The hybrid solution reduces logic resource cost and provides an effective custom configurable solution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.