Method and system for enhancing the endurance of memory cells
US7257668B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2006 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Jun 14, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes a plurality of non-volatile memory cells associated with a plurality of flag cells storing managing data. The managing data of the flag cells forms a data set. The data set is utilized to determine to which memory cell of the plurality of memory cells to write new data and from which of the memory cells to read currently stored data. The data set is changed to a different data set whenever a new value is written to a designated memory cell to indicate an alternate memory cell to be written to next and an alternate memory cell to be read from next. The data set may be changed by alternately writing a new value to a different flag cell in each successive change of the data set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.