Dynamic reconfiguration of cache memory
US7257678B2 · kind B2 · utility
19Cited by
10References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2004 |
| Grant date | Aug 14, 2007 |
| Priority date | — |
| Expiry date | Sep 16, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processing node includes a plurality of processor cores each including a cache memory coupled to a cache monitor unit and to a configuration unit. Each cache monitor unit may be configured to independently monitor a current utilization of the cache memory to which it is coupled and to determine whether the current utilization is below a predetermined utilization value. The configuration unit may selectably disable one or more portions of the cache memory in response to the cache monitor unit determining that the current utilization is below the predetermined utilization value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.